 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G SST34HF324G32Mb Dual-Bank Flash + 4 Mb SRAM MCP ComboMemory Data Sheet FEATURES: * Flash Organization: 2M x16 - 32 Mbit: 24Mbit + 8Mbit * Concurrent Operation - Read from or Write to SRAM while Erase/Program Flash * SRAM Organization: - 4 Mbit: 256K x16 * Single 2.7-3.3V Read and Write Operations * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: (typical values @ 5 MHz) - Active Current: Flash 10 mA (typical) SRAM 6 mA (typical) - Standby Current: 10 A (typical) * Hardware Sector Protection (WP#) - Protects 4 outer most sectors (8 KWord) in the smaller bank by holding WP# low and unprotects by holding WP# high * Hardware Reset Pin (RST#) - Resets the internal state machine to reading data array * Sector-Erase Capability - Uniform 2 KWord sectors * Block-Erase Capability - Uniform 32 KWord blocks * Read Access Time - Flash: 70 ns - SRAM: 70 ns * Erase-Suspend / Erase-Resume Capabilities * Latched Address and Data * Fast Erase and Word-Program (typical): - Sector-Erase Time: 18 ms - Block-Erase Time: 18 ms - Chip-Erase Time: 35 ms - Program Time: 7 s * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard Command Set * Packages Available - 48-ball LFBGA (6mm x 8mm) * All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST34HF324G ComboMemory devices integrate a 2M x16 CMOS flash memory bank with 256K x16 CMOS SRAM memory bank in a multi-chip package (MCP). These devices are fabricated using SST's proprietary, highperformance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF324G devices are ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF324G devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high-performance Program operations, the flash memory banks provide a typical Pro(c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 1 gram time of 7 sec. The entire flash memory bank can be erased and programmed word-by-word in 4 seconds (typically) for the SST34HF324G, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST34HF324G devices contain on-chip hardware and software data protection schemes. The flash and SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The SRAM bank enable signal, BES#, selects the SRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. See Table 3 for memory organization. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF324G are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. See Figure 2 for pin assignments. Flash Program Operation These devices are programmed on a word-by-word basis. Before programming, one must ensure that the sector which is being programmed is fully erased. The Program operation is accomplished in three steps: Device Operation The SST34HF324G use BES# and BEF# to control operation of either the flash or the SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES# is low the SRAM is activated for Read and Write operation. BEF# and BES# cannot be at low level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES# bank enables are raised to VIHC (Logic High) or when BEF# is high. 1. Software Data Protection is initiated using the three-byte load sequence. 2. Address and data are loaded. During the Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. 3. The internal Program operation is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed typically within 7 s. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during an internal Program operation are ignored. Concurrent Read/Write Operation The SST34HF324G provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. This allows data alteration code to be executed from SRAM, while altering the data in flash. The following table lists all valid states. Concurrent Read/Write State Table Flash Program/Erase Program/Erase SRAM Read Write Flash Sector- /Block-Erase Operation These devices offer both Sector-Erase and Block-Erase operations. These operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on a uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. Any commands issued during the Block- or SectorErase operation are ignored except Erase-Suspend and Erase-Resume. See Figures 12 and 13 for timing waveforms. The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Flash Read Operation The Read operation of the SST34HF324G is controlled by BEF# and OE#, both have to be low for the system to obtain data from the outputs. BEF# is used for device selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6). (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 2 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet Flash Chip-Erase Operation The SST34HF324G provide a Chip-Erase operation, which allows the user to erase all sectors/blocks to the "1" state. This is useful when the device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bits or Data# Polling. See Table 6 for the command sequence, Figure 11 for timing diagram, and Figure 23 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Flash Data# Polling (DQ7) When the device is in an internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or BEF#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or BEF#) pulse. See Figure 9 for Data# Polling (DQ7) timing diagram and Figure 21 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "1"s and "0"s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The toggle bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operations. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to "1" if a Read operation is attempted on an Erase-suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bit information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of a Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 21 for a flowchart. Flash Erase-Suspend/-Resume Operations The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode within 20 s after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at "1". While in Erase-Suspend mode, a Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended, the system must issue an Erase-Resume command. The operation is executed by issuing a one-byte command sequence with Erase Resume command (30H) at any address in the one-byte sequence. Flash Write Operation Status Detection The SST34HF324G provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 3 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TABLE 1: Write Operation Status Status Normal Operation Standard Program Standard Erase EraseSuspend Mode Read From Erase Suspended Sector/ Block Read From Non-Erase Suspended Sector/ Block Program DQ7 DQ7# 0 1 DQ6 Toggle Toggle 1 DQ2 No Toggle Toggle Toggle Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 17). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 16). The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. See Figures 16 and 17 for timing diagrams. Software Data Protection (SDP) The SST34HF324G provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST34HF324G are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15DQ8 are "Don't Care" during any SDP command sequence. Data Data Data DQ7# Toggle No Toggle T1.0 1310 Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. Data Protection The SST34HF324G provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Hardware Block Protection The SST34HF324G provide a hardware block protection which protects the outermost 8 KWord in Bank 1. The block is protected when WP# is held low. See Figure 3 for BlockProtection location. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed. (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 4 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet Product Identification The Product Identification mode identifies the device as SST34HF324G and the manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 5 and 6 for software operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 22 for the ID Entry command sequence flowchart. TABLE 2: Product Identification ADDRESS Manufacturer's ID Device ID SST34HF324G Note: BK = Bank Address (A20-A18) SRAM Operation With BES# low and BEF# high, the SST34HF324G operates as either 256K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. When BES# and BEF# are high, all memory banks are deselected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 5 for SRAM Read and Write data byte control modes of operation. SRAM Read The SRAM Read operation of the SST34HF324G is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. BES# is used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 3, for further details. SRAM Write The SRAM Write operation of the SST34HF324G is controlled by WE# and BES#, both have to be low for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE# whichever occurs first. The write time is measured from the last falling edge of BES# or WE# to the first rising edge of BES# or WE#. Refer to the Write cycle timing diagrams, Figures 4 and 5, for further details. DATA 00BFH 7353H T2.0 1310 BK0000H BK0001H Product Identification Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 15 for timing waveform and Figure 22 for a flowchart. (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 5 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet A20- A0 Address Buffers SuperFlash Memory (Bank 1) WP# RST# BEF# LBS# UBS# WE# OE# BES# SuperFlash Memory (Bank 2) Control Logic I/O Buffers DQ15 - DQ0 Address Buffers 4 Mbit SRAM 1310 B1.0 FIGURE 1: Functional Block Diagram (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 6 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TABLE 3: Dual-Bank Memory Organization (1 of 2) SST34HF324G Block BA63 BA62 BA61 BA60 BA59 BA58 BA57 Bank 1 BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 Bank 2 BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 Block Size 8 KW / 16 KB 24 KW / 48 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB Address Range x8 3FC000H-3FFFFFH 3F0000H-3FBFFFH 3E0000H-3EFFFFH 3D0000H-3DFFFFH 3C0000H-3CFFFFH 3B0000H-3BFFFFH 3A0000H-3AFFFFH 390000H-39FFFFH 380000H-38FFFFH 370000H-37FFFFH 360000H-36FFFFH 350000H-35FFFFH 340000H-34FFFFH 330000H-33FFFFH 320000H-32FFFFH 310000H-31FFFFH 300000H-30FFFFH 2F0000H-2FFFFFH 2E0000H-2EFFFFH 2D0000H-2DFFFFH 2C0000H-2CFFFFH 2B0000H-2BFFFFH 2A0000H--2AFFFFH 290000H--29FFFFH 280000H--28FFFFH 270000H--27FFFFH 260000H--26FFFFH 250000H--25FFFFH 240000H--24FFFFH 230000H--23FFFFH 220000H--22FFFFH 210000H--21FFFFH 200000H--20FFFFH 1F0000H--1FFFFFH 1E0000H--1EFFFFH 1D0000H--1DFFFFH 1C0000H--1CFFFFH 1B0000H--1BFFFFH 1A0000H--1AFFFFH 190000H--19FFFFH 180000H--18FFFFH 170000H--17FFFFH 160000H--16FFFFH Address Range x16 1FE000H-1FFFFFH 1F8000H-1FDFFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B8000H-1BFFFFH 1B0000H-1B7FFFH 1A8000H-1AFFFFH 1A0000H-1A7FFFH 198000H-19FFFFH 190000H-197FFFH 188000H-18FFFFH 180000H-187FFFH 178000H-17FFFFH 170000H-177FFFH 168000H-16FFFFH 160000H-167FFFH 158000H-15FFFFH 150000H-157FFFH 148000H-14FFFFH 140000H-147FFFH 138000H-13FFFFH 130000H-137FFFH 128000H-12FFFFH 120000H-127FFFH 118000H-11FFFFH 110000H-117FFFH 108000H-10FFFFH 100000H-107FFFH 0F8000H-0FFFFFH 0F0000H-0F7FFFH 0E8000H-0EFFFFH 0E0000H-0E7FFFH 0D8000H-0DFFFFH 0D0000H-0D7FFFH 0C8000H-0CFFFFH 0C0000H-0C7FFFH 0B8000H-0BFFFFH 0B0000H-0B7FFFH (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 7 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TABLE 3: Dual-Bank Memory Organization (Continued) (2 of 2) SST34HF324G Block BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 Bank 2 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 Block Size 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB Address Range x8 150000H--15FFFFH 140000H--14FFFFH 130000H--13FFFFH 120000H--12FFFFH 110000H--11FFFFH 100000H--10FFFFH 0F0000H--0FFFFFH 0E0000H--0EFFFFH 0D0000H--0DFFFFH 0C0000H--0CFFFFH 0B0000H--0BFFFFH 0A0000H--0AFFFFH 090000H--09FFFFH 080000H--08FFFFH 070000H--07FFFFH 060000H--06FFFFH 050000H-05FFFFH 040000H-04FFFFH 030000H-03FFFFH 020000H-02FFFFH 010000H-01FFFFH 000000H-00FFFFH Address Range x16 0A8000H-0AFFFFH 0A0000H-0A7FFFH 098000H-09FFFFH 090000H-097FFFH 088000H-08FFFFH 080000H-087FFFH 078000H-07FFFFH 070000H-077FFFH 068000H-06FFFFH 060000H-067FFFH 058000H-05FFFFH 050000H-057FFFH 048000H-04FFFFH 040000H-047FFFH 038000H-03FFFFH 030000H-037FFFH 028000H-02FFFFH 020000H-027FFFH 018000H-01FFFFH 010000H-017FFFH 008000H-00FFFFH 000000H-007FFFH T3.0 1310 TOP VIEW (balls facing down) SST34HF324G 6 5 4 A13 A9 A12 A8 A14 A10 A15 A11 A16 UBS# DQ15 VSS DQ7 DQ14 DQ13 DQ6 DQ5 DQ12 VDD DQ4 DQ2 DQ10 DQ11 DQ3 DQ0 DQ8 DQ9 DQ1 A0 BEF# OE# VSS 1310 48-lfbga L3K P1a.0 WE# RST# LBS# A19 3 BES# WP# A18 A6 A2 A20 A5 A1 2 A7 A17 A4 1 A3 A B C D E F G H FIGURE 2: Pin Assignments for 48-ball LFBGA (6mm x 8mm) (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 8 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TABLE 4: Pin Description Symbol AMS1 to A0 DQ15-DQ0 Pin Name Address Inputs Data Inputs/Outputs Functions To provide Flash address, A20-A0. To provide SRAM address, A17-A0 To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE#, BES#, and BEF# are high. To activate the Flash memory bank when BEF# is low To activate the SRAM memory bank when BES# is low To gate the data output buffers To control the Write operations To enable DQ15-DQ8 To enable DQ7-DQ0 To protect and unprotect the bottom 8 KWord (4 sectors) from Erase or Program operation To Reset and return the device to Read mode 2.7-3.3V Power Supply T4.0 1310 BEF# BES# OE# WE# UBS# LBS# WP# RST# VSS Flash Memory Bank Enable SRAM Memory Bank Enable Output Enable Write Enable Upper Byte Control (SRAM) Lower Byte Control (SRAM) Write Protect Reset Ground Power Supply VDD 1. AMS = Most Significant Address (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 9 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TABLE 5: Operational Modes Selection for SRAM Mode Full Standby Output Disable BEF#1 VIH VIH VIL Flash Read Flash Write Flash Erase SRAM Read VIL VIL VIL VIH BES#1,2 VIH X VIL VIL VIH X VIH X VIH X VIH X VIL VIL VIH VIL VIH VIL SRAM Write VIH VIL X VIL VIL VIH VIL Product Identification3 1. 2. 3. 4. OE#2 X X VIH X VIH VIL VIH VIH WE#2 X X VIH X VIH VIH VIL VIL LBS#2 X X X VIH X X X X UBS#2 X X X VIH X X X X VIL VIL VIH VIL VIL VIH X DQ15-0 HIGH-Z HIGH-Z HIGH-Z DOUT DIN X DOUT HIGH-Z DOUT DIN HIGH-Z DIN HIGH-Z HIGH-Z HIGH-Z DOUT DIN X DOUT DOUT HIGH-Z DIN DIN HIGH-Z DQ15-8 HIGH-Z HIGH-Z HIGH-Z DQ15-8=HIGH-Z DQ15-8=HIGH-Z X DOUT DOUT HIGH-Z DIN DIN HIGH-Z VIL VIH VIL VIH X Manufacturer's ID4 Device ID4 T5.0 1310 Do not apply BEF# = VIL and BES# = VIL at the same time X can be VIL or VIH, but no other value. Software mode only With A20-A18 = VIL; SST Manufacturer's ID = BFH, is read with A0=0, SST34HF324G Device ID = 7353H, is read with A0=1 (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 10 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TABLE 6: Software Command Sequence Command Sequence Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Software ID Entry5 1st Bus Write Cycle Addr1 555H 555H 555H 555H XXXXH XXXXH 555H 555H XXH 2nd Bus Write Cycle Addr1 2AAH 2AAH 2AAH 2AAH 3rd Bus Write Cycle Addr1 555H 555H 555H 555H 4th Bus Write Cycle Addr1 WA3 555H 555H 555H 5th Bus Write Cycle Addr1 2AAH 2AAH 2AAH 6th Bus Write Cycle Addr1 SAX4 BAX 4 Data2 AAH AAH AAH AAH B0H 30H AAH AAH F0H Data2 55H 55H 55H 55H Data2 A0H 80H 80H 80H Data2 Data AAH AAH AAH Data2 55H 55H 55H Data2 50H 30H 10H 555H 2AAH 2AAH 55H 55H BKX6 555H 555H 90H F0H Software ID Exit Software ID Exit 1. 2. 3. 4. T6.0 1310 Address format A10-A0 (Hex), Addresses A20-A11 can be VIL or VIH, but no other value, for the command sequence. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence WA = Program word address SAX for Sector-Erase; uses A20-A11 address lines BAX for Block-Erase; uses A20-A15 address lines BKx for Bank address; uses A20-A15 address lines 5. The device does not remain in Software Product Identification mode if powered down. 6. A20-A18 = VIL Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. Operating Range Range Commercial Extended Ambient Temp 0C to +70C -20C to +85C VDD 2.7-3.3V 2.7-3.3V AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 18 and 19 (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 11 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TABLE 7: DC Operating Characteristics (VDD = VDDF and VDDS = 2.7-3.3V) Limits Symbol IDD1 Parameter Active VDD Current Read Flash SRAM Concurrent Operation Write2 Flash SRAM ISB IRT ILI ILIW ILO VIL VILC VIH VIHC VOL VOH Standby VDD Current Reset VDD Current Input Leakage Current Input Leakage Current on WP# pin and RST# pin Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Flash and SRAM Output Low Voltage Flash and SRAM Output High Voltage 0.7 VDD 40 30 30 30 1 10 10 0.8 0.3 mA mA A A A A A V V V V 0.2 V V 15 10 45 mA mA mA Min Max Units Test Conditions Address input = VILT/VIHT, at f=5 MHz, VDD=VDD Max, all DQs open OE#=VIL, WE#=VIH BEF#=VIL, BES#=VIH BEF#=VIH, BES#=VIL BEF#=VIH, BES#=VIL WE#=VIL BEF#=VIL, BES#=VIH, OE#=VIH BEF#=VIH, BES#=VIL VDD = VDD Max, BEF#=BES#=VIHC RST#=GND VIN=GND to VDD, VDD=VDD Max WP#=GND to VDD, VDD=VDD Max RST#=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min T7.0 1310 VDD-0.3 VDD-0.2 1. See Figure 18 2. IDD active while Erase or Program is in progress. (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 12 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TABLE 8: Recommended System Power-up Timings Symbol TPU-READ1 TPU-WRITE 1 Parameter Power-up to Read Operation Power-up to Write Operation Minimum 100 100 Units s s T8.0 1310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: Capacitance (Ta = 25C, f=1 Mhz, other pins open) Parameter CI/O1 CIN 1 Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 20 pF 16 pF T9.0 1310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: Flash Reliability Characteristics Symbol NEND TDR1 ILTH1 1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 T10.0 1310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 13 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet AC CHARACTERISTICS TABLE 11: SRAM Read Cycle Timing Parameters Symbol TRCS TAAS TBES TOES TBYES TBLZS1 TOLZS1 TBYLZS1 TBHZS 1 Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time BES# to Active Output Output Enable to Active Output UBS#, LBS# to Active Output BES# to High-Z Output Output Disable to High-Z Output Min 70 Max 70 70 35 70 Units ns ns ns ns ns ns ns ns 0 0 0 25 25 35 10 ns ns ns ns T11.0 1310 TOHZS1 TBYHZS TOHS 1 UBS#, LBS# to High-Z Output Output Hold from Address Change 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: SRAM Write Cycle Timing Parameters Symbol TWCS TBWS TAWS TASTS TWPS TWRS TBYWS TODWS TOEWS TDSS TDHS Parameter Write Cycle Time Bank Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# to End-of-Write Output Disable from WE# Low Output Enable from WE# High Data Set-up Time Data Hold from Write Time 0 30 0 Min 70 60 60 0 60 0 60 30 Max Units ns ns ns ns ns ns ns ns ns ns ns T12.0 1310 (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 14 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TABLE 13: Flash Read Cycle Timing Parameters VDD = 2.7-3.3V Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP TRY 1,2 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time BEF# Low to Active Output OE# Low to Active Output BEF# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change RST# Pulse Width RST# High Before Read RST# Pin Low to Read Min 70 Max 70 70 35 Units ns ns ns ns ns ns 0 0 16 16 0 500 50 20 ns ns ns ns ns s T13.0 1310 TRHR1,2 1,2,3 1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 2. L3K package only 3. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase. TABLE 14: Flash Program/Erase Cycle Timing Parameters Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH1 TIDA TES TBR TSE TBE TSCE 1 1 1 Parameter Program Time Address Setup Time Address Hold Time WE# and BEF# Setup Time WE# and BEF# Hold Time OE# High Setup Time OE# High Hold Time BEF# Pulse Width WE# Pulse Width WE# Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Erase-Suspend Latency Bus# Recovery Time Sector-Erase Block-Erase Chip-Erase Min 0 40 0 0 0 10 40 40 30 30 30 0 Max 12 Units s ns ns ns ns ns ns ns ns ns ns ns ns TCPH1 150 10 1 25 25 50 ns s s ms ms ms T14.1 1310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 15 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TRCS ADDRESSES AMSS-0 TAAS BES# TBES TBLZS OE# TOLZS UBS#, LBS# TBYLZS DQ15-0 DATA VALID 1310 F02.0 TOHS TBHZS TOES TOHZS TBYES TBYHZS Note: AMSS = Most Significant Address AMSS = A17 for SST34HF324G FIGURE 3: SRAM Read Cycle Timing Diagram TWCS ADDRESSES AMSS3-0 WE# TAWS TASTS TWPS TWRS TBWS BES# UBS#, LBS# TODWS DQ15-8, DQ7-0 NOTE 2 TBYWS TDSS TOEWS TDHS NOTE 2 1310 F03.0 VALID DATA IN Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES# goes low coincident with or after WE# goes low, the output will remain at high impedance. If BES# goes high coincident with or before WE# goes high, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A17 for SST34HF324G FIGURE 4: SRAM Write Cycle Timing Diagram (WE# Controlled) (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 16 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TWCS ADDRESSES AMSS3-0 TWPS WE# TBWS BES# TAWS TASTS UBS#, LBS# TDSS DQ15-8, DQ7-0 NOTE 2 TWRS TBYWS TDHS NOTE 2 1310 F04.0 VALID DATA IN Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A17 for SST34HF324G FIGURE 5: SRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled) TRC ADDRESS A20-0 TCE BEF# TOE OE# VIH WE# TCLZ TOH DATA VALID TOLZ TAA TOHZ TCHZ HIGH-Z DATA VALID 1310 F05.0 DQ15-0 HIGH-Z FIGURE 6: Flash Read Cycle Timing Diagram (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 17 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet TBP ADDRESS A20-0 555 TAH TWP WE# TAS OE# TCH BEF# TCS? DQ15-0 XXAA XX55 XXA0 TDS TDH DATA WORD (ADDR/DATA) Note: X can be VIL or VIH, but no other value. 1310 F06.0 2AA 555 ADDR TWPH VALID FIGURE 7: Flash WE# Controlled Program Cycle Timing Diagram TBP ADDRESS A20-0 555 TAH TCP BEF# TAS OE# TCH TDS TDH XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: X can be VIL or VIH, but no other value. 1310 F07.0 2AA 555 ADDR TCPH WE# TCS? DQ15-0 VALID FIGURE 8: Flash BEF# Controlled Program Cycle Timing Diagram (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 18 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet ADDRESS A20-0 TCE BEF# TOEH OE# TOE WE# TOES DQ7 DATA DATA# DATA# DATA 1310 F08.0 FIGURE 9: Flash Data# Polling Timing Diagram ADDRESS A20-0 TCE BEF# TOEH OE# TOE WE# TBR DQ6 TWO READ CYCLES WITH SAME OUTPUTS 1310 F09.0 VALID DATA FIGURE 10: Flash Toggle Bit Timing Diagram (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 19 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet SIX-BYTE CODE FOR CHIP-ERASE ADDRESS A20-0 555 2AA 555 555 2AA 555 TSCE BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 VALID 1310 F10.0 Note: This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.) X can be VIL or VIH, but no other value. FIGURE 11: Flash WE# Controlled Chip-Erase Timing Diagram SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A20-0 BEF# 555 2AA 555 555 2AA BAX TBE OE# TWP WE# XXAA XX55 XX80 XXAA XX55 XX30 DQ15-0 VALID 1310 F11.0 Note: This device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.) BAX = Block Address X can be VIL or VIH, but no other value. FIGURE 12: Flash WE# Controlled Block-Erase Timing Diagram (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 20 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A20-0 BEF# OE# TWP WE# 555 2AA 555 555 2AA SAX TSE DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 VALID 1310 F12.0 Note: This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.) SAX = Sector Address X can be VIL or VIH, but no other value. FIGURE 13: Flash WE# Controlled Sector-Erase Timing Diagram Three-Byte Sequence For Software ID Entry 555 2AA 555 0000 0001 ADDRESSES BEF# OE# TWP WE# TWPH DQ15-0 XXAA XX55 XX90 TAA 00BF Device ID 1310 F13.0 TIDA Note: X can be VIL or VIH, but no other value. Device ID - 7353H for SST34HF324G FIGURE 14: Flash Software ID Entry and Read (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 21 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESSES 555 2AA 555 DQ15-0 XXAA XX55 XXF0 TIDA CE# OE# TWP WE# TWPH 1310 F14.0 Note: X can be VIL or VIH, but no other value. FIGURE 15: Flash Software ID Exit (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 22 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet RY/BY# 0V RST# TRP BEF#/OE# TRHR 1310 F15.0 FIGURE 16: RST# Timing (when no internal operation is in progress) TRY RY/BY# RST# TRP BEF# TBR OE# 1310 F16.0 FIGURE 17: RST# Timing (during Sector- or Block-Erase operation) (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 23 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet VIHT INPUT? VILT 1310 F17.0 VIT REFERENCE POINTS VOT OUTPUT AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 18: AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1310 F18.0 FIGURE 19: A Test Load Example (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 24 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Address/Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1310 F19.0 Note: X can be VIL or VIH, but no other value. FIGURE 20: Program Algorithm (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 25 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet Internal Timer Program/Erase Initiated Toggle Bit Program/Erase Initiated Data# Polling Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read byte/word Read DQ7 Program/Erase Completed Read same byte/word No Is DQ7 = true data? Yes No Does DQ6 match? Yes Program/Erase Completed Program/Erase Completed 1310 F20.0 FIGURE 21: Wait Options (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 26 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet Software Product ID Entry Command Sequence Software ID Exit Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX90H Address: 555 Load data: XXF0H Address: 555H Wait TIDA Wait TIDA Read Software ID Return to normal operation 1310 F21.0 Note: X can be VIL or VIH, but no other value. FIGURE 22: Software Product ID Command Flowcharts (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 27 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet Chip-Erase Command Sequence Load data: XXAAH Address: 555H Sector-Erase Command Sequence Load data: XXAAH Address: 555H Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX10H Address: 555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1310 F22.0 Note: X can be VIL or VIH, but no other value. FIGURE 23: Erase Command Sequence (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 28 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet PRODUCT ORDERING INFORMATION Device Speed Suffix1 XX Suffix2 XXXX Package Attribute E1 = non-Pb Package Modifier K = 48 balls Package Type L3 = LFBGA (6mm x 8mm x 1.4mm, 0.45mm ball size) Temperature Range C = Commercial = 0C to +70C E = Extended = -20C to +85C Minimum Endurance 4 =10,000 cycles Read Access Speed 70 = 70 ns Version G = Flash WP# and RST# + SRAM SRAM Density 4 = 4 Mbit Flash Density 32 = 32Mbit Voltage H = 2.7-3.3V Product Series 34 = Dual-Bank Flash + SRAM ComboMemory SST34HF324G - XXX 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". Valid combinations for SST34HF324G SST34HF324G-70-4C-L3KE SST34HF324G-70-4E-L3KE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 29 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G Data Sheet PACKAGING DIAGRAMS TOP VIEW 8.00 0.20 BOTTOM VIEW 5.60 0.80 0.45 0.05 (48X) 6 5 4 3 2 1 0.80 ABCDEFGH A1 CORNER HGFEDCBA 4.00 6.00 0.20 6 5 4 3 2 1 A1 CORNER 1.30 0.10 SIDE VIEW SEATING PLANE 0.35 0.05 0.12 1mm Note: 1. Except for total height dimension, complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-lfbga-L3K-6x8-450mic-5 48-ball Low-profile, Fine-pitch Ball Grid Array (LFBGA) 6mm x 8mm SST Package Code: L3K TABLE 15: Revision History Number 00 Description Date Jun 2006 * Initial Release Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 30 |
Price & Availability of SST34HF324G-70-4E-L3KE
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |